John,
We could extend my proposal with another instruction.
How about an EX(ecute) Immediate on Condition (EXIC) instruction?
In assembler, the instruction would be written as --
EXIC M1,R2
In memory, the instruction would have the following layout --
0-7 Opcode
8-11 M1
12-15 R2
16-31 Reserved
M1 is a condition code mask, as is commonly used in a BC or JC instruction.
If the bit contained in the mask corresponding to the current condition code
is set, then the instruction immediately following the EXIC instruction will
be executed. Otherwise, the instruction will act as a NOP (4700 0000).
R2 is a general purpose register. If non-zero, the low-order byte of the
register will be inclusively or'ed into bits 8-15 of the instruction
immediately following the EXIC before it is executed. Like the standard
EX(ecute) instruction, this operation occurs in the instruction processor
and does not affect the memory containing the instruction specified by the
I3 operand.
This instruction will not set a condition code. However, the EX(ecuted)
instruction may set the condition code.
John P. Baker
President
NGSSA, LLC
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:[email protected]]
On Behalf Of John McKown
Sent: Monday, November 26, 2012 7:43 PM
To: [email protected]
Subject: Re: Stupid? though on a new "execute" instruction.
Very nice. I still kind of like the idea that the EXecuted instruction is
the next one in the source code and I-cache and is auto-skipped or some sort
of a NOP.
Ah, silliness. And, given how IBM seems to be deprecating the use of
assembler by "pushing" Metal C, not likely to be considered. Unless one of
the compiler writers, who seem to be driving some of the newest opcode
development, come up with a compelling need for such a thing. But I consider
that to be doubtful.
--
John McKown
Maranatha! <><
