Instructions are hard to count, though instruction count isn't a very good way to determine CISCness.
RISC tends to have a small number of instruction lengths, often 1. S/360 through z/ have three lengths. Not too CISCy, but not RISC. (VAX might have 14 or so, from one byte on up.) RISC tends to minimize address modes. Some have been added lately, but the largest fraction of instructions executed should still be RR or RX. Not too CISCy, but not so RISCy, either. VAX has many address modes, 21 on the list that I have, but 14 of those also have an indexed mode, so it should be 35. And there can be more than one such address per instruction. (Many operands are register only, but I am pretty sure that there are some where two operands can have one of those 35.) Many RISC systems try to execute every instruction in one cycle. That brought things like MULTIPLY_STEP, an instruction that did part of a multiply, but that had to be executed many times to do an actual multiply. Most try to avoid this now. There are some pretty complicated instructions even from S/360, and many complicated ones added later, which are pretty CISCy. Still, in terms of instruction length and address modes, not so bad. Since S/360 through z/ use different opcodes for different addressing modes of the same instruction, do you count those as separate instructions, or just one? (Compare to VAX, where there is an opcode byte and address mode byte.) -- glen
