I think he means the CC bits.
Gary Weinhold
Senior Application Architect
DATAKINETICS | Data Performance & Optimization
Phone +1.613.523.5500 x216
Email: [email protected]
Visit us online at www.DKL.com
E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system.
__________
On 2016-04-04 11:33, Robin Vowels wrote:
----- Original Message ----- From: "Ed Jaffe"
<[email protected]>
Sent: Tuesday, April 05, 2016 12:50 AM
On 4/4/2016 7:24 AM, Gary Weinhold wrote:
Even if there's no actual performance difference for these
instructions, wouldn't the "not setting the CC" possibly improve the
pipeline, since the hardware knows the next conditional branch does
not have to wait for this instruction to be evaluated for affecting
the CC?
Indeed! Avoiding CC "interlock" is exactly why an entire suite of
"compare and branch" instructions were created! :-)
However, that should not apply in this situation since SLR sets the
CC in exactly the same way as all other logical subtract
instructions. Both SR and SLR set the CC. Only the meaning of the
bits is different.
Um, the bits are all zero after clearing the register with SR and SLR
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
