----- Original Message -----
From: "Ed Jaffe" <[email protected]>
Sent: Tuesday, April 05, 2016 12:50 AM
On 4/4/2016 7:24 AM, Gary Weinhold wrote:
Even if there's no actual performance difference for these
instructions, wouldn't the "not setting the CC" possibly improve the
pipeline, since the hardware knows the next conditional branch does
not have to wait for this instruction to be evaluated for affecting
the CC?
Indeed! Avoiding CC "interlock" is exactly why an entire suite of
"compare and branch" instructions were created! :-)
However, that should not apply in this situation since SLR sets the CC
in exactly the same way as all other logical subtract instructions. Both
SR and SLR set the CC. Only the meaning of the bits is different.
Um, the bits are all zero after clearing the register with SR and SLR
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