Ed, Is there any chance you could provide (maybe eventually in a SHARE session presentation?) a set of good examples of using the vector instructions as you say you do?
Or am I late to the party and there have already been such SHARE sessions that I missed? If I have one particular beef with the PoOPS writing team it is that there are significant sets of instructions with no usage examples, z13+ vector instructions being only just the latest. Peter -----Original Message----- From: IBM Mainframe Assembler List <[email protected]> On Behalf Of Ed Jaffe Sent: Sunday, June 7, 2020 10:48 AM To: [email protected] Subject: Re: Does the z architecture have something like the SIMD instructions On 6/7/2020 7:11 AM, Peter Relson wrote: > That limitation is not the case for z/Architecture vector operations. > </snip> > > I erred in writing that. Shmuel was of course correct. The "vector > register" is 128 bits (one quadword). > The extent of the "vectorization" depends on the size of the operands. We use SIMD *heavily* for character-based operations and the speed is incredible! Doing 16 operations at once sure is preferable to doing just one! ijs... ;-) -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
