There has been a lot of discussion about the representation of signed binary integers and the common operations of signed addition and subtraction on these items.
Since the introduction of the S/360 and continuing on through all of its largely compatible successors, the representation of signed binary integers has remained the same. For the sake of clarity I am going to paraphrase some of the text found in the original S/360 Principles of Operation and the z/Architecture Principles of Operation. A negative number is represented by the two's complement of the positive number of the same absolute value. The two's complement of a number is obtained by forming the one's complement of the number (i.e., inverting all of the bits), adding a value of one in the rightmost bit position, allowing a carry into the sign position, and ignoring any carry out of the sign position. The notation for signed binary integers has a number range in which, for a given length (number of bits), the set of negative nonzero numbers is one larger than the set of positive nonzero numbers. The number "zero" is represented by all zero bits. The two's complement of zero is zero; there is no "negative zero". The maximum positive number consists of a sign bit of zero followed by all ones; the maximum negative number (the negative number with the greatest absolute value) consists of a sign bit of one followed by all zeros. The two's complement of the maximum negative number cannot be represented in the same number of bits. When an operation, such as Load Complement, attempts to produce the two's complement of the maximum negative number, the result is the maximum negative number, and a fixed-point overflow exception is recognized. An overflow does not result, however, when the maximum negative number is complemented as an intermediate result but the final result is within the representable range. An example of this case is a subtraction of the maximum negative number from -1. A fixed-point overflow condition exists for signed binary addition or subtraction when the carry out of the sign-bit position and the carry out of the leftmost numeric bit position disagree. Detection of an overflow does not affect the result produced by the operation. In other words, signed addition and subtraction produce a fixed-point overflow when the result is outside the range of representation for signed binary integers. Considering the various Add and Subtract instructions which operate on 32-bit signed binary integers, there is an overflow when the proper result would be greater than or equal to +2**31 or less than -2**31. The actual result stored after an overflow differs from the proper result by 2**32. The various Add and Subtract instructions which operate on Unsigned binary integers of the same length (for example Add Logical) produce the same results as the corresponding Signed instructions. The instructions differ only in the interpretation of the result. Add interprets the result as a signed binary integer and inspects it for sign, magnitude, and overflow to set the condition code accordingly and, for an overflow condition, potentially cause a Fixed-Point Overflow Program Check interruption. Add Logical interprets the result as an unsigned binary integer and sets the condition code according to whether the result is zero and whether there was a carry out of the high order bit. Such a carry is not considered an overflow, and no program check interruption for overflow can occur. To illustrate the behavior of two's complement operations let's use 8-bit values (the operations behave exactly the same way for fixed point binary integers with a larger number of bits). The maximum positive number is: B'0111 1111' = x'7F' = 127 decimal The maximum negative number is: B'1000 0000' = x'80' = -128 decimal The two's complement of the maximum negative number: Step 1. Invert all of the bits: B'1 000 0000' becomes B'0 111 1111' Step 2. Add 1 to the result obtained in Step 1. B'0 111 1111' + B'0 000 0001' ------------ B'1 000 0000' An overflow condition is recognized because a carry out of the leftmost numeric bit (the carry out of bit 1 into the sign bit is a 1) and the carry out of the sign bit (this carry out is a zero) are different. In other words, the overflow condition is recognized because the proper result would be greater than or equal to +2**7 (decimal 128). The resultant number remains unchanged. The resultant number differs from the proper result by 2**8 (2**8 = decimal 256; 256-128=128).
