Mark yes, it worked but why? I still need the entire instruction in SETCs João Reginato (61) 9911-55500
Em ter., 14 de nov. de 2023 às 18:27, Mark Hammack <[email protected]> escreveu: > This worked but may not be what you need: > > MACRO > &LABEL ZERO &N > &OPCODE SETC 'SR' > &REST SETC '&OPCODE &N,&N' > &LABEL &OPCODE &N,&N > MEND > > > > > *Mark* > > > On Tue, Nov 14, 2023 at 3:20 PM Willy Jensen <[email protected]> > wrote: > > > Would a sublisted SETC do, where P(1) is the instruction and P(2) is the > > register? > > > > -----Oprindelig meddelelse----- > > Fra: IBM Mainframe Assembler List <[email protected]> På > > vegne af João Reginato > > Sendt: 14. november 2023 22:16 > > Til: [email protected] > > Emne: Re: ASMA057E Undefined operation code SR 15,15 > > > > without the SETC it works but I need it to simplify the logic of a bigger > > macro. > > . > > João Reginato > > (61) 9911-55500 > > > > > > Em ter., 14 de nov. de 2023 às 18:08, Paul Gilmartin < > > [email protected]> escreveu: > > > > > On 11/14/23 13:58:30, João Reginato wrote: > > > > Gil > > > > > > > > I know it works in the way you've proposed but I need to use the > > > > SETC in > > > a > > > > very bigger macro. > > > >. > > > Please post an example showing the failure without the SETC. > > > > > > Would it be better to have two separate MACROs, one of which calls the > > > other? > > > > > > >> Em ter., 14 de nov. de 2023 às 17:46, Paul Gilmartin escreve:>>>> . > > > >>> I believe the SETC is unnecessary. How a bout just: > > > >>> MACRO > > > >>> &REST ZERO &N > > > >>> &REST SR &N,&N > > > >>> MEND > > > >>> > > > >>> START > > > >>> L ZERO 15 > > > >>> END > > > > > > -- > > > gil > > > > > >
