I suspect that is what he meant. Note that it's signed.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
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________________________________________
From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> on behalf
of Binyamin Dissen <00001773bcccb823-dmarc-requ...@listserv.uga.edu>
Sent: Wednesday, February 26, 2025 9:05 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: BCTG Instruction
External Message: Use Caution
Did you perhaps wish to use
BRCTG
?
But that doesn't use a base register. The I2 field is the number of halfwords
offset from the instruction.
On Wed, 26 Feb 2025 07:51:39 -0500 Joe Reichman <reichman...@gmail.com> wrote:
:>Hi
:>
:>
:>My understanding of this new instruction is that it is a BCT with a new 20
:>bit displacement.
:>
:>The object code layout of this6 byte instruction has in bit 20 - 31 the 12
:>bit displacement and if the address exceeds 4096 decimal the new bit
:>displacement would get populated in bits
:>
:>32 - 40
:>
:>I tried out a BCTG R9,LONGDISP
:>
:>Where the address of longdisp was beyond 4096 and yet I don't see bits 32 -
:>40 of the instruction being populated
:>
:> So here is the example
:>
:>LONGDISP is beyond 4,096 and in bits 31 - 40 there is zeros
:>
:>
:>00A0 LONGDISP DS 0H
:>
:> 2E60 E390 00A0 00 46 BCTG R9,LONGDISP
:>
--
Binyamin Dissen <bdis...@dissensoftware.com>
http://secure-web.cisco.com/10VvBXXP13I9QdFmSqp2I-Ib4_bsUk1XQkyAoTHK6iKBL-9V_SoZUmE6Ah9XPIWUfh4utzXEsjM1WIwl4pvjXn2_sKGIcrw1PR1P-jL2-c1P55KN20OYJpv9QnekdN57NXSt5Mxz4CzSZKTK5NgKVUSBdmYiR370gKKvXJ0FDoSrBdw6E_vNXYaTD3FPK0eQaUSnk1bV5Unku0FtMuyMnqH6Zw4KT-2cugodLTddAAAb4UwpMnQ9lk31kDyapEgRqmx03VcVMGMmFH0dQs9QirorclZQwOuXMMmS7jUs4PG8c7bZvIWi1S7h28RWx_CY3urbNq_f7Lsd1bRHuJeo9ygtkQ0Cnl89znmA6icxTZ6OKONXVD5UpMPQbeFnlYkZFd5dYKRiLunO35XhepByfYamd6dnnnbUyO_1Z52DdScU/http%3A%2F%2Fwww.dissensoftware.com
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