Did the PSW associated with the 0C4 point to the RP instruction (either start or end), indicating a problem with that instruction itself, or to the resume PSW address from the second operand?
Could instruction execute protection be relevant here? If it is enabled, storage acquired with GETMAIN RU/RC (SVC 120) or the STORAGE equivalent is non-executable by default, so if either the RP or the resume address is in storage dynamically acquired in that way then you could get an 0C4 for that reason. Jonathan Scott -----Original Message----- From: IBM Mainframe Assembler List <[email protected]> On Behalf Of Robert Crawford Sent: 20 October 2025 15:44 To: [email protected] Subject: Re: Resume Program (RP) Unfortunately, I don't have any breadcrumbs for R15's old value. However, I was able use the offsets in the RP's parameter list to work backwards to its original value. Now it all flanges up except for my understanding where the 0C4 came from. The instruction that's the target of the resume is referring to key 8 storage which matches the PSW's program key. The base register address in the instruction is valid for both 24 and 31-bit addressing. The PSW is in 31-bit addressing mode. Thanks for everyone's replies.
