You need to order the TM tests with the most-bits-on flag value first followed by the next-highest-count-of-bits-on value, etc.
As Mark suggested, maybe you really want CLI instead of TM in this case? Peter From: IBM Mainframe Assembler List <[email protected]> On Behalf Of David Clark Sent: Monday, February 16, 2026 2:46 PM To: [email protected] Subject: Apparent Test Under Mask Failure Can someone please explain to me how the following fails to drop through to the actual test for C5? The request at d'8000' is 'E' (x'C5', b'11000101') but the code is taking the 'D' (x'C4', b'11000100') branch. Why? The condition code should result in mixed -- not ones. Am I going to have to change from bit mask testing to 'CLI' testing? 000872 91C4 8000 00000 1842+ TM REQU_DELETE,L'REQU_DELETE 000876 A714 0124 00ABE 1843+ JO TXTDLET ...snip... 0008C2 91C5 8000 00000 1994+ TM REQU_2EBCDIC,L'REQU_2EBCDIC 0008C6 A714 02D7 00E74 1995+ JO TXT2EBC The bit mask flags are defined as follows--using my own macros based on the late Dr. John Ehrman's SHARE presentation on the subject. 000000 300=TXTREQU DS CL1 00000 000C4 308+REQU_DELETE EQU *-1,C'D' 00000 000C5 310+REQU_2EBCDIC EQU *-1,C'E' ...snip... Sincerely, Dave Clark -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
