Exactly and thats why feeding the DAC klock backwards as someone has
done it in the DIY section is the way to go. Pity the s/pdif wasn't
specifyed like this to begin with.

Patrick Dixon;194712 Wrote: 
> Because the buffer is filling at nominally the same rate as it's
> emptying.  If the buffer was capable of being filled much faster, and
> filling could be stopped and started (a bit like streaming over tcp),
> it's easy, but if you try to design a buffer for SPDIF you have to
> overcome the overfilling and emptying issues, or 'adjust' the read
> clock to compensate.


-- 
jonte0
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