bigfool1956;254041 Wrote: > So I'm reading through the article that Sean posted a link to in the > "Setting Transporter to Slave for World Clock Input" thread, and I > notice a small point that the author made when he was describing > measuring clock jitter. > > In there he says it can take up to several hours for a clock to warm up > and settle down - which, as I understand it, means that during this > period jitter levels would be greatly increased. > > So, I'm wondering how long does t take for the clock in the tp to > settle down, and also is it kept 'warm and cosily settled' when in > standby mode?
I have not seen jitter decrease as something warms up. Actually, the notion that electronics need to "warm up" is a widely held holdover from the tube days, but as far as solid state electronics are concerned it is generally wrong. Thermal noise actually (obviously?) increases with temperature. Now, if you are talking about the _mean_ frequency of a crystal clock at a given point in time, yes, this will vary as a function of temperature. But that is not really what is meant by jitter (phase noise). Really it means that for optimal clock accuracy it must be calibrated to a particular temperature. "Ovenized" oscillators address this requirement for applications which need clock stability across very long periods of times, but it's not going to improve jitter. See here: http://www.isotemp.com/146-005.html If your instrument is measuring pulse widths in the time domain, and you first calibrate it to some value and then start taking measurements relative to that value, then as the crystal slowly drifts, say, higher in frequency, you will start to see smaller and smaller pulse widths relative to that first measured value. But this is not phase noise - it is equivalent to a DC (or very low frequency) offset in an analog signal. If you were measuring cycle-to-cycle jitter, or if you were at least comparing against a recently taken mean value, then you would not see it as such. For the measurement setup described in the article it would be important for the frequency to be extremely stable in order to get a valid measurement, because the crystal is being measured against a PLL, and any slow drift of the crystal would appear as continuous phase noise because the narrow bandwidth of the PLL makes it lag behind. NB to be pedantic yes a clock that is drifting slowly will of course have a continuous change in cycle-to-cycle timing. But this is dwarfed by the actual jitter that would normally be present. For example, a clock drifting from 1.000 MHz to 1.001 MHz over a period of ten seconds: Ten seconds worth of cycles at the median frequency of 1.00050 MHz = 10,005,000 cycles. Beginning period: 1/1,000,000 = 1.000000 us Ending period: 1/1,001,000 = 0.999001 us So the period has changed by one nanosecond over the course of 10 million cycles. Therefore the cycle-to-cycle difference attributable to the drift would be 1ns / 10E-6 == 1.0*10E-16 == 100 attoseconds. That's a tenth of a femtosecond, or a ten thousandth of a picosecond. A good oscillator might be considered anything having less than 100ps rms jitter. -- seanadams ------------------------------------------------------------------------ seanadams's Profile: http://forums.slimdevices.com/member.php?userid=3 View this thread: http://forums.slimdevices.com/showthread.php?t=41729 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
