On Mon, 7 Dec 2015 11:27:44 +0100 Sascha Hauer <[email protected]> wrote:
> On Sun, Dec 06, 2015 at 05:50:51PM +0300, Antony Pavlov wrote: > > On Fri, 4 Sep 2015 08:20:48 +0200 > > Sascha Hauer <[email protected]> wrote: > > > > > On Fri, Aug 28, 2015 at 06:46:14PM +0300, Antony Pavlov wrote: > > > > On Fri, 28 Aug 2015 08:34:32 +0200 > > > > Sascha Hauer <[email protected]> wrote: > > > > > > > > > On Fri, Aug 28, 2015 at 01:24:04AM +0300, Antony Pavlov wrote: > > > > > > N.B. phys_to_virt() translates phys address > > > > > > to KSEG1 (uncached) address as barebox mips > > > > > > has no cache support. > > > > > > > > > > What would it take to implement cache support for mips? > > > > lack of the cache support is critical problem for current barebox mips > > > > support. > > > > I'm planning to add cache support in several weeks. > > > > This task needs much test efforts for different boards. > > > > > > > > Anyway I can't carry out cache adding work at one. > > > > But adding virt_to_phys and DMA support will help to add cache support > > > > one day anyway. > > > > > > Looking at this again the virt_to_phys/phys_to_virt macros are not > > > necessary. dma_alloc_coherent() already returns both the virtual address > > > and the DMA address. It should be possible to replace DMA_ADDRESS_BROKEN > > > in the ehci driver with a real pointer and use it appropriatly in the > > > driver. > > > > > > > I have tried to get physical address from dma_alloc_coherent(), > > here is a small part of my patch (just for demonstration): > > > > --- a/drivers/usb/host/ehci-hcd.c > > +++ b/drivers/usb/host/ehci-hcd.c > > @@ -41,6 +41,7 @@ struct ehci_priv { > > struct ehci_hcor *hcor; > > struct usb_host host; > > struct QH *qh_list; > > + dma_addr_t qh_list_dma; > > struct qTD *td; > > int portreset; > > unsigned long flags; > > @@ -403,7 +410,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long > > pipe, void *buffer, > > goto fail; > > } > > > > - ehci->qh_list->qh_link = cpu_to_hc32((uint32_t)ehci->qh_list | > > QH_LINK_TYPE_QH); > > + ehci->qh_list->qh_link = cpu_to_hc32(ehci->qh_list_dma | > > QH_LINK_TYPE_QH); > > > > token = hc32_to_cpu(qh->qt_token); > > if (!(token & 0x80)) { > > @@ -1306,7 +1313,7 @@ int ehci_register(struct device_d *dev, struct > > ehci_data *data) > > ehci->post_init = data->post_init; > > > > ehci->qh_list = dma_alloc_coherent(sizeof(struct QH) * NUM_TD, > > - DMA_ADDRESS_BROKEN); > > + &ehci->qh_list_dma); > > ehci->periodic_queue = dma_alloc_coherent(sizeof(struct QH), > > DMA_ADDRESS_BROKEN); > > ehci->td = dma_alloc_coherent(sizeof(struct qTD) * NUM_TD, > > > > > > However ehci_td_buffer() gets buf pointer outside of ehci driver (e.g. via > > usb_bulk_msg()), > > so it is difficult to avoid virt_to_phys() in ehci_td_buffer(), e.g.: > > > > @@ -195,7 +197,7 @@ static int ehci_td_buffer(struct qTD *td, void *buf, > > size_t sz) > > > > idx = 0; > > while (idx < 5) { > > - td->qt_buffer[idx] = cpu_to_hc32(addr); > > + td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys(addr)); > > next = (addr + 4096) & ~4095; > > delta = next - addr; > > if (delta >= sz) > > > > Have you any idea? > > No. Translating this addres into a physical address seems unavoidable > here. I would still prefer a real cache implementation for MIPS though. > Have you looked further into that? The current MIPS cached/uncached > memory windows seem to be a constant source of problems we could avoid. We already have Atheros AR9331 branch with cache support. I assume that cleaned MIPS cache support patch series will be ready till Christmas. -- Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
