This patch is based on 0e9a87bb from the linux-imx kernel: ------------------------------------------------------------------------------ | ARM/MP: 814220—B-Cache maintenance by set/way operations can execute | out of order. | | Description: | The v7 ARM states that all cache and branch predictor maintenance operations | that do not specify an address execute, relative to each other, in program | order. However, because of this erratum, an L2 set/way cache maintenance | operation can overtake an L1 set/way cache maintenance operation, this would | cause the data corruption. | | This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. | | This patch is the SW workaround by adding a DSB before changing cache levels | as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. | Signed-off-by: Jason Liu <[email protected]> ------------------------------------------------------------------------------
It was later posted to LKML for Linux inclusion, but is not yet mainline: <[email protected]> Unlike the Linux version, we don't make the barrier dependent on a Kconfig option and always execute the dsb: On 25/4/19 12:02, Lucas Stach wrote: > I don't think we need a Kconfig option here. This function is not > really performance critical. The short pipeline stall introduced by the > dsb when switching the cache level is minor compared to the time it > takes to actually move the cache blocks on a clean. > > Just always execute the [dsb] and add a comment on why it is needed. Signed-off-by: Ahmad Fatoum <[email protected]> --- arch/arm/cpu/cache-armv7.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 7a1c5c01894c..9487dd03f6cc 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -120,6 +120,7 @@ THUMB( ite eq ) skip: add r12, r12, #2 @ increment cache number cmp r3, r12 + dsb @ work-around Cortex-A7 erratum 814220 bgt loop1 finished: ldmfd sp!, {r4-r11} -- 2.20.1 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
