On Thu, Apr 25, 2019 at 04:32:28PM +0200, Ahmad Fatoum wrote: > This series fixes a number of potential caching issues with armv7. > > They are: > > - Cortex-A7 erratum #814220 > Because of this erratum, the CPU may reorder cache maintenance operations > when it shouldn't. > - Wrong Cache invalidation order for Cortex-A7 > On the Cortex-A7, the L2 cache needs to be invalidated before the L1 cache. > - Device memory isn't marked NX (Never eXecute) > NX prevents the CPU instruction prefetcher from inadvertently > accessing memory mapped devices
Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
