Hi Johannes, On Mon, Apr 28, 2025 at 07:20:01PM +0200, johannes@gnu-linux.rocks wrote: > I have a Cora Z7 board which I want to port to barebox. The Cora Z7 embeds an > Zynq 7000 SoC with a single core Cortex-A9 and 512 MB DDR3 memory. Barebox > already supports the Zynq 7000 and the Avnet Zedboard. > > I have some questions and maybe you can point me in the right direction: > > When I am compiling barebox with the zynq_defconfig, as an output I get the > file > barebox-avnet-zedboard.img. This file contains the PBL, barebox proper and the > device tree, right?
Right. > > The Cora Z7 uses a different memory configuration compared to the Zedboard. My > first idea was to use Xilinx FSBL and let the FSBL start barebox. The FSBL can > start an ELF file. But if I use just the compiled barebox file, the device > tree > is missing, right? In case of the Zedboard you could take start_avnet_zedboard.pbl. This contains all necessary components including device tree and barebox proper. However, this binary is linked to 0x0 and the FSBL will likely load it there. I don't know where the FSBL itself is located. > Is there a way to hard code the UART to use for the barebox > console for barebox proper? Why do you want to hardcode it? Setting the console via device tree is just fine. For debugging your early code I recommend CONFIG_DEBUG_LL. For zynq the UART is hardcoded to ZYNQ_UART1_BASE_ADDR in include/mach/zynq/debug_ll.h. You can change it in this file. With CONFIG_DEBUG_LL enabled you can put putc_ll() in your code. > > The Zynq on the Cora Z7 only embeds a single core Cortex A9 while the SoC on > the > Zedboard embeds a dual core Cortex A9. Does this affect the cores > initialization > in arch/arm/mach_zynq? I don't think so. I haven't used Zynq myself though. Regards, Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
