Am Thu, May 01, 2025 at 02:16:44PM +0200 schrieb Johannes Roith: > Hi, > > thanks for the fast replies. > > Am Tue, Apr 29, 2025 at 11:49:40AM +0200 schrieb Ahmad Fatoum: > > Hi, > > > > On 4/29/25 10:34, Sascha Hauer wrote: > > > In case of the Zedboard you could take start_avnet_zedboard.pbl. This > > > contains all necessary components including device tree and barebox > > > proper. > > > > > > However, this binary is linked to 0x0 and the FSBL will likely load it > > > there. I don't know where the FSBL itself is located. > > Can I change the address to which barebox is linked to? E.g. in Vitis > the application is linked to 0x10000 and the FSBL starting this > application to 0x0. > > > > > The pbl files tend to be a bit bigger, because they are meant only > > as input to objcopy. You can add to images/Makefile.zynq, e.g. > > > > image-$(CONFIG_MACH_ZEDBOARD) += start_avnet_zedboard.elf > > > > And it will generate a much more compact ELF file that should > > be interchangeable (I had tested this on ZynqMP). > > > > >> Is there a way to hard code the UART to use for the barebox > > >> console for barebox proper? > > > > > > Why do you want to hardcode it? Setting the console via device tree is > > > just fine. > > > > > > For debugging your early code I recommend CONFIG_DEBUG_LL. For zynq the > > > UART is hardcoded to ZYNQ_UART1_BASE_ADDR in include/mach/zynq/debug_ll.h. > > > You can change it in this file. > > > > > > With CONFIG_DEBUG_LL enabled you can put putc_ll() in your code. > > > > CONFIG_DEBUG_PBL is also often useful. > > > > >> The Zynq on the Cora Z7 only embeds a single core Cortex A9 while the > > >> SoC on the > > >> Zedboard embeds a dual core Cortex A9. Does this affect the cores > > >> initialization > > >> in arch/arm/mach_zynq? > > > > > > I don't think so. I haven't used Zynq myself though. > > > > Cheers, > > Ahmad > > > > > > > > Regards, > > > Sascha > > > > > > > -- > > Pengutronix e.K. | | > > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > > > > The good news is, I can boot barebox (PBL and proper) now and sometimes > also can Linux. Here is the output of my barebox: > > Digilent Cora Z7 PBL > uncompress.c: memory at 0x00000000, size 0x20000000 > mmu: enabling MMU, ttb @ 0x1ffd0000 > endmem = 0x20000000 > arm_mem_scratch = 0x1fff8000+0x00008000 > arm_mem_stack = 0x1ffe9000+0x0000f000 > arm_mem_ttb = 0x1ffd0000+0x00010000 > arm_mem_barebox_image = 0x1fe00000+0x00200000 > arm_mem_early_malloc = 0x1fde0000+0x00020000 > membase = 0x00000000+0x20000000 > uncompress.c: uncompressing barebox binary at 0x00006270 (size 0x00029c0c) to > 0x1fe00000 (uncompressed size: 0x0006c0e8) > uncompress.c: jumping to uncompressed image at 0x1fe00000 > > > barebox 2025.04.0-00215-gdacb19ae3252-dirty #11 Wed Apr 30 22:22:15 CEST 2025 > > > Board: Digilent Cora Z7 > ERROR: could not get clock /axi/dma-controller@f8003000:apb_pclk(0) > ERROR: could not get clock /axi/etb@f8801000:apb_pclk(0) > ERROR: could not get clock /axi/tpiu@f8803000:apb_pclk(0) > ERROR: could not get clock /axi/funnel@f8804000:apb_pclk(0) > ERROR: could not get clock /axi/ptm@f889c000:apb_pclk(0) > ERROR: could not get clock /axi/ptm@f889d000:apb_pclk(0) > mdio_bus: miibus0: probed > macb e000b000.ether...@e000b000.of: Cadence GEM at 0xe000b000 > arasan-sdhci e0100000....@e0100000.of: registered as mmc0 > malloc space: 0x17e00000 -> 0x1fdfffff (size 128 MiB) > arasan-sdhci e0100000....@e0100000.of: error while transferring data for > command 6 > arasan-sdhci e0100000....@e0100000.of: state = 0x01f70202 , interrupt = > 0x00208000 > mmc0: Card's startup fails with -74 > barebox-environment chosen:environment-sd.of: probe failed: No such file or > directory > environment load /dev/env0: No such file or directory > Maybe you have to create the partition. > > > Do you know what to do about the "could not get clock errors"? Do I have > to take care about them or just ignore them? > > The more critical error comes from the SD card. Every second boot I am > getting the errors shown above, sometimes the card is started correctly. > > Also when barebox can startup the mmc0, when starting the Linux Kernel > sometimes the rootfs on /dev/mmcblk0p2 is not found and the SD Card is > not detected. So, there seems to be something wrong with the SD Card > interface...
Maybe because I missed the rootwait argument for the Linux Kernel Commandline... > > In lowlevel.c I am setting the clock divider for the sdio0 interface to 10 > and the Source for generated clock is IO PLL. Therefore, the sdio IP > should get a 100 MHz input clock. IS this correct? Do you know which > clockrate the driver expects? > > Or do you have any other idea what could case the error? Ok, I found out that maybe 100 MHz is a little bit to slow for this SD Card IP. When setting the clock to 200 MHz or 250 MHz, the mmc0 gets detected all the time by barebox. > > In case I can fix the remaining errors I would like to bring the changes > upstream and send a patch. Here I also have some questions: > > I added the following files and folder: > > arch/arm/boards/digilent-cora/ > arch/arm/dts/zynq-cora.dts > dts/src/arm/xilinx/zynq-cora.dts > > arch/arm/boards/digilent-cora/ is a copy of arch/arm/boards/avnet-zed/ > with my changes applied. In the Copyright, should I keep the existing > name and just add mine as a second author? > > If I understand it correctly, the files in dts/src are imported from the > Linux kernel git repo, right? In this case I should try to bring my > modified device tree mainline to Linux first and then commit my changes > to barebox? Or is there another file location I can drop my device tree > temporarily until it is available in Linux? > > And a last question: How can I change the default boot method in barebox > from net to mmc0? > > Thanks and best regards, > Johannes >
