From: Alexander Shiyan <[email protected]> Explicitly configure CPLL frequency to 1500 MHz to ensure system stability and reliable operation. The change aligns with Rockchip's recommended practices for clock configuration in embedded systems using RK3588 SoCs.
Signed-off-by: Alexander Shiyan <[email protected]> Link: https://lore.barebox.org/[email protected] Signed-off-by: Sascha Hauer <[email protected]> (cherry picked from commit 09c87c85e098fdfcec00200b68c8ae285e1cd47c) Signed-off-by: Ahmad Fatoum <[email protected]> --- arch/arm/dts/rk3588.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index 416700cf0ecd..42d692a9bdd1 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -1,6 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) / { + assigned-clocks = <&cru PLL_CPLL>; + assigned-clock-rates = <1500000000>; + dmc: memory-controller { compatible = "rockchip,rk3588-dmc"; rockchip,pmu = <&pmu1grf>; -- 2.47.3
