After changing the cntfrq register the global PBL clocksource must be re-initialized. The inline assembly was dropped in favor of the set_cntfrq function, the subsequent read is a no-op and dropped without a replacement.
Signed-off-by: Stefan Kerkmann <[email protected]> --- arch/arm/mach-socfpga/agilex5-clock-manager.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/agilex5-clock-manager.c b/arch/arm/mach-socfpga/agilex5-clock-manager.c index 4ce7a2d4a2..0b0425efc1 100644 --- a/arch/arm/mach-socfpga/agilex5-clock-manager.c +++ b/arch/arm/mach-socfpga/agilex5-clock-manager.c @@ -5,6 +5,7 @@ #include <common.h> #include <io.h> +#include <asm/hardware/arm_architected_timer.h> #include <asm/system.h> #include <dt-bindings/clock/intel,agilex5-clkmgr.h> #include <linux/bitops.h> @@ -252,8 +253,6 @@ static void clk_basic_init(struct socfpga_clk_plat *plat, { u32 vcocalib; u32 cntfrq = COUNTER_FREQUENCY_REAL; - u32 counter_freq = 0; - if (!cfg) return; @@ -361,8 +360,8 @@ static void clk_basic_init(struct socfpga_clk_plat *plat, /* Update with accurate clock frequency */ if (current_el() == 3) { - asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); - asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq)); + set_cntfrq(cntfrq); + arm_arch_timer_init(cntfrq); } /* Out of boot mode */ -- 2.47.3
