From: Sascha Hauer <[email protected]> clk: imx: pll14xx: Use register defines consistently The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CTL to DIV_CTL0 because that's the name in the reference manual.
Signed-off-by: Sascha Hauer <[email protected]> [ ahmad: ported from Linux 485b4ff57c27, s/(readl|writel)_relaxed/\1/ ] Signed-off-by: Ahmad Fatoum <[email protected]> --- drivers/clk/imx/clk-pll14xx.c | 49 ++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 8a773f19f807..c1d5a6b88f41 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -19,7 +19,8 @@ #include "clk.h" #define GNRL_CTL 0x0 -#define DIV_CTL 0x4 +#define DIV_CTL0 0x4 +#define DIV_CTL1 0x8 #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -118,7 +119,7 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_div; u64 fvco = parent_rate; - pll_div = readl(pll->base + 4); + pll_div = readl(pll->base + DIV_CTL0); mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; @@ -137,8 +138,8 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, short int kdiv; u64 fvco = parent_rate; - pll_div_ctl0 = readl(pll->base + 4); - pll_div_ctl1 = readl(pll->base + 8); + pll_div_ctl0 = readl(pll->base + DIV_CTL0); + pll_div_ctl1 = readl(pll->base + DIV_CTL1); mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; @@ -168,7 +169,7 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { u32 val; - return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, + return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, LOCK_TIMEOUT_US); } @@ -187,32 +188,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl(pll->base + 4); + tmp = readl(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel(tmp, pll->base + 4); + writel(tmp, pll->base + DIV_CTL0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl(pll->base); + tmp = readl(pll->base + GNRL_CTL); tmp |= LOCK_SEL_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Enable RST */ tmp &= ~RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel(div_val, pll->base + 0x4); + writel(div_val, pll->base + DIV_CTL0); /* * According to SPEC, t3 - t2 need to be greater than @@ -224,7 +225,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -233,7 +234,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); return 0; } @@ -269,32 +270,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl(pll->base + 4); + tmp = readl(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel(tmp, pll->base + 4); + writel(tmp, pll->base + DIV_CTL0); tmp = rate->kdiv << KDIV_SHIFT; - writel(tmp, pll->base + 8); + writel(tmp, pll->base + DIV_CTL1); return 0; } /* Enable RST */ - tmp = readl(pll->base); + tmp = readl(pll->base + GNRL_CTL); tmp &= ~RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel(div_val, pll->base + 0x4); - writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); + writel(div_val, pll->base + DIV_CTL0); + writel(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than @@ -306,7 +307,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -315,7 +316,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); return 0; } -- 2.47.3
