barebox never touches NOC_CLK_ROOT on the i.MX8MM and i.MX8MN in the PBL, so early startup uses the ROM's setting: sys_pll1_800m with a post divider of 2, i.e. 400MHz.
barebox proper later reparents NOC to sys_pll3_out as requested by the upstream device tree, but the assigned rate is 0 and clk-conf only switches the mux, so the ROM's divider stays and NOC runs at half the SYS_PLL3 rate: 300MHz instead of 600MHz on the i.MX8MN. This was observed to make an L2 cache miss about 10% more costly. U-Boot's clock_init() instead writes NOC_CLK_ROOT in full: undivided sys_pll3_out, i.e. 750MHz on the i.MX8MM and 600MHz on the i.MX8MN, both within the 800MHz maximum of the root. Let's do the same in barebox. Reported-by: Niels de Koeijer <[email protected]> Signed-off-by: Ahmad Fatoum <[email protected]> --- arch/arm/mach-imx/imx8m.c | 5 +++++ include/mach/imx/imx8m-ccm-regs.h | 1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 3b2833a07ec2..533e2877237f 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -124,6 +124,11 @@ static void __imx8m_early_clock_init(int cpu_type) imx8m_clock_set_target_val(IMX8M_NOC_IO_CLK_ROOT, IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_CCM_TARGET_ROOTn_MUX(2)); + } else { + /* NOC from undivided sys_pll3_out */ + imx8m_clock_set_target_val(IMX8M_NOC_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(2)); } clrsetbits_le32(ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_ARM_A53_CLK_ROOT), diff --git a/include/mach/imx/imx8m-ccm-regs.h b/include/mach/imx/imx8m-ccm-regs.h index 035cd13ed694..42d0c485f25b 100644 --- a/include/mach/imx/imx8m-ccm-regs.h +++ b/include/mach/imx/imx8m-ccm-regs.h @@ -22,6 +22,7 @@ * Applications Processor Reference Manual */ #define IMX8M_ARM_A53_CLK_ROOT 0 +#define IMX8M_NOC_CLK_ROOT 26 #define IMX8M_NOC_IO_CLK_ROOT 27 #define IMX8M_DRAM_SEL_CFG 48 #define IMX8M_DRAM_ALT_CLK_ROOT 64 -- 2.47.3
