On Fri, 02 Oct 2026 13:35:46 +0200, Ahmad Fatoum wrote:
> While clk_pll1416x_early_set_rate() programs the dividers, waits for
> the lock and clears the bypass, it doesn't actually ungate the clock.
>
> Therefore, the i.MX8M early clock init sets the CLKE bit by hand
> afterwards, but it does so only for the ARM PLL.
> SYS_PLL3 is reconfigured without CLKE being touched, because it works
> out, because it's set at reset and BootROM doesn't clear it.
>
> [...]
Applied, thanks!
[1/5] clk: imx: pll14xx: enable PLL output in clk_pll1416x_early_set_rate()
https://git.pengutronix.de/cgit/barebox/commit/?id=2386a6205654 (link may
not be stable)
[2/5] ARM: i.MX8MM/8MN: clock NOC from SYS_PLL3 in early clock init
https://git.pengutronix.de/cgit/barebox/commit/?id=8831f6ac48bd (link may
not be stable)
[3/5] ARM: i.MX8M: feed A53 cores from ARM PLL via CORE_SEL_CFG in early clock
init
https://git.pengutronix.de/cgit/barebox/commit/?id=cb021545c98d (link may
not be stable)
[4/5] ARM: i.MX8M: source dram_apb from sys_pll2_200m in early clock init
https://git.pengutronix.de/cgit/barebox/commit/?id=d8e671542d09 (link may
not be stable)
[5/5] ARM: i.MX8M: order early clock init like U-Boot
https://git.pengutronix.de/cgit/barebox/commit/?id=a13bb80f62af (link may
not be stable)
Best regards,
--
Sascha Hauer <[email protected]>
