Am Sonntag, 21. Dezember 2014 12:19:08 UTC+1 schrieb Lenny: > > The ADC can definitely sample at 1.6 MHz, that is four channels could go > up to 400 kHz each (sequentially). The 1.6 MHz correspond to the minimal 15 > steps for one sample when setting the ADC clock to 24 MHz, that is, setting > the CLKDIV register to zero, and not to 7 as it is set by default (which > explains your 200kHz theoretical sampling rate). I have my own assembler > code which works, but as it is a bit older, it is not in line with newer > things like libpruio. If you want to have a look at my code to get it > working let me know and I'll send it to you. >
Hi Lenny, which hardware do you refer to? On my Beaglebone Black the register ADC_CLKDIV is 0 (zero) by default. And yes, it's true, that each single step samples at 1.6 MHz. But when I trigger the ADC subsystem by software and restart the step sequence (write to register STEPENABLE) at more than 250 kHz, the timing gets inaccurate. It doesn't matter how many steps are active. That's why I limit the sum-sampling rate to 200 kHz in libpruio to be at the save site (200 kHz also mentioned in the TI TRM). BR -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
