I have to say, the motivation to remove caps suddenly makes a lot more sense to me after actually observing the power-on reset sequence on the scope:
Horizontal scale: 5ms per grid line, 1ms per minor tick Vertical range 0-4V, scale: 0.8V per grid line, 0.2V per minor tick (except the yellow line which measures current, not well-calibrated but roughly: Vertical range 0-640mA, scale: 128mA per grid line, 32mA per minor tick) Blue, cyan are regulated supplies (this beagle has a unified 3V3 <https://groups.google.com/d/msg/beagleboard/7sxPePT7wkM/_oNSCta5WusJ>), green is PGOOD (power-on reset release), orange is SYS_RESETn. The power-on sequencing by the PMIC (strobes 1-5) is located entirely in the first two grid blocks, with the modest bumps before 1V8 and after 3V3 are due to the first and last supplies ramped up (neither visible here). Normally one would expect logic signals to have faster rise times than power supply ramp-ups, but instead the reset signal has such a big RC-time that you can nearly fit the complete power-up sequence in one! True, all parties that care have smith-trigger inputs, but somehow I can't shake a feeling of discomfort looking at this graph... I'd still be more inclined to increase the amount of pull-up than risk noise-sensitivity by removing the caps though (and/or at least leave the small cap in place). I do see a potential issue here however: the PHY documentation says the reset edge of reset should occur no sooner than 25 ms after the power supplies are up. Even with the big RC it's cutting things awefully close, especially since the PHY specs a minimum rising-edge voltage threshold of 0.81V. The good part is that the phy doesn't require reset to be low all this time, it just requires a proper reset some time after the power supplies have come up. The bad part is that thanks to being wired to SYS_RESETn, the only way to reset the phy is by performing a warm reset. SPL could of course just do exactly that if it detects the reset cause was a cold (power-on) reset. The ugly part is that the PHY requires a reset pulse of at least 100 μs, while the AM335x generates one about 10 μs if you configure RSTTIME1 (in PRM_DEVICE) to its max value, so you still need to rely on the RC-network to stretch it long enough (though it can be orders of magnitude smaller than it is now). Please, next time connect PHY reset to a GPIO instead? (You can free up a pin by discarding the eMMC reset, it's useless and unused anyway.) Matthijs -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
