Thanks! Could you tell me where is the cap on the board? Already read the 
BBGW's SCH, but still couldn't figure it out....
And do you think this is the problem caused by specific kernel versions 
(I'm using ubuntu 16.04, 4.4.12-ti-r30)? I assume using SPI0 for 
communication is really common among BBGW users, but after I searched the 
whole forum, just you and me encountered this CLK hardware design issue??   

On Friday, December 2, 2016 at 12:43:24 AM UTC+8, Joe Phaneuf wrote:
> Howdy, correct, had to completely remove the cap on the spi0 clock. Hope 
> that helps!

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