The 100pF cap, C204, seems to me to be almost useless without a series bead 
(or resistor) to divide down the EMI signal (2.4GHz).

That said, if UART2 pin is re-purposed as SPI_CLK, then I agree that C204 
could be problematic.

---
David McRell

On Saturday, December 3, 2016 at 7:28:30 AM UTC-6, Buming Chen wrote:
>
> Thank you very much! I will try to remove it and see if any luck with the 
> spi0....
>
> On Sat, Dec 3, 2016 at 1:09 AM, Joe Phaneuf <j...@verdigris.co 
> <javascript:>> wrote:
>
>> Pretty confident it's not kernel version. Actually explored that line of 
>> thinking a little, but there's a u-boot spi tool you can use to test before 
>> the kernel even loads, and you can replicate this issue with that.
>>
>> FYI response from Seeed regarding the existence of the caps is that 
>> they're for EMC related to the UART on the Grove connector.
>>
>> This is the location of the spi0 capacitors (Should only need to remove 
>> the one on clock, but I removed both, forget which one is which).  Near the 
>> sd card slot, underneath the grove connectors:
>>
>>
>> <https://lh3.googleusercontent.com/-uE8y1zCNuvY/WEGpUUGI9_I/AAAAAAAAAhs/UtQrknyZH3ExCItVhhWf_-_sveyWlE1fACLcB/s1600/BBGW.jpg>
>>
>>
>> On Thursday, December 1, 2016 at 10:16:14 PM UTC-8, Buming Chen wrote:
>>>
>>> Thanks! Could you tell me where is the cap on the board? Already read 
>>> the BBGW's SCH, but still couldn't figure it out....
>>> And do you think this is the problem caused by specific kernel versions 
>>> (I'm using ubuntu 16.04, 4.4.12-ti-r30)? I assume using SPI0 for 
>>> communication is really common among BBGW users, but after I searched the 
>>> whole forum, just you and me encountered this CLK hardware design issue??   
>>>
>>> On Friday, December 2, 2016 at 12:43:24 AM UTC+8, Joe Phaneuf wrote:
>>>>
>>>> Howdy, correct, had to completely remove the cap on the spi0 clock. 
>>>> Hope that helps!
>>>>
>>> -- 
>> For more options, visit http://beagleboard.org/discuss
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>
>
>
> -- 
> *Buming Chen*
>

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