Hi,
I'm reading LTC2500-32 ADCs with the PRU. The LTC2500 delivers 32 Bits
every usecond
as a 320nsec burst with 100 MHz bit rate. I receive the burst with a
shift register in a
Xilinx CoolrunnerII CPLD and read the shift register bytewise with PRU2.
I think I could read 3 ADCs with the current timing (minimum requirement
for me),
maybe 4 with some optimization. The PRU writes the data into this 12 KW
shared ram,
organized as a ping-pong buffer. The ARM reads continuously half of the
buffer while
the other half is written by the PRU. That also solves the problem that
is is hard
to allocate REALLY big buffers in the virtual address space of Linux and
fixing
their location somewhere for the PRU, in addition to the unpredictable
duration
of a memory cycle when competing with the ARM for access.
I have currently paused that software development to first fix the
analog part.
Cheers, Gerhard
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