That is really interesting Gerhard!! Let me ask you, why did you decide to use a CPLD instead any other device?
Actually this signal configuration is very common in ADC+Serdes devices (ADCs with DDR bit clock), in example you can take a look at these application notes: http://www.ti.com/lit/an/sbaa205/sbaa205.pdf https://www.xilinx.com/support/documentation/application_notes/xapp866.pdf My idea is, if possible, to do just that with PRUs as a more powerful, lower cost, better integrated setup. On Friday, May 29, 2020 at 9:13:20 PM UTC+2, Gerhard Hoffmann wrote: > > Hi, > > I'm reading LTC2500-32 ADCs with the PRU. The LTC2500 delivers 32 Bits > every usecond > > as a 320nsec burst with 100 MHz bit rate. I receive the burst with a > shift register in a > > Xilinx CoolrunnerII CPLD and read the shift register bytewise with PRU2. > > I think I could read 3 ADCs with the current timing (minimum requirement > for me), > > maybe 4 with some optimization. The PRU writes the data into this 12 KW > shared ram, > > organized as a ping-pong buffer. The ARM reads continuously half of the > buffer while > > the other half is written by the PRU. That also solves the problem that > is is hard > > to allocate REALLY big buffers in the virtual address space of Linux and > fixing > > their location somewhere for the PRU, in addition to the unpredictable > duration > > of a memory cycle when competing with the ARM for access. > > I have currently paused that software development to first fix the > analog part. > > > Cheers, Gerhard > > > > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/0bb2f408-61fa-4c19-9eff-42c6f5b0cc73%40googlegroups.com.
