The SPARC T5 is surprisingly good here, with a very short path to cache
and a moderate number of threads with hot cache lines. Cache
performance was one of the surprises when the slowish early T-machines
came out, and surprised a smarter colleague and I who had apps
bottlenecking on cold cache lines on what were nominally much faster
processors.
I'd love to have a T5-1 on an experimenter board, or perhaps even in my
laptop (I used to own a SPARC laptop), but that's not where Snoracle is
going.
--dave
On 05/01/16 02:37 PM, Dave Täht wrote:
On 1/5/16 11:29 AM, Steinar H. Gunderson wrote:
On Tue, Jan 05, 2016 at 10:57:13AM -0800, Dave Täht wrote:
Context switch time is probably one of the biggest hidden nightmares in
modern OOO cpu architectures - they only go fast in a straight line. I'd
love to see a 1ghz processor that could context switch in 5 cycles.
It's called hyperthreading? ;-)
Anyway, the biggest cost of a context switch isn't necessarily the time used
to set up registers and such. It's increased L1 pressure; your CPU is now
running different code and looking at (largely) different data.
+10.
A L1/L2 Icache dedicated to interrupt processing code could make a great
deal of difference, if only cpu makers and benchmarkers would make
CS time something we valued.
Dcache, not so much, except for the intel architectures which are now
doing DMA direct to cache. (any arms doing that?)
/* Steinar */
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