On Tue, 5 Jan 2016 11:37:02 -0800 Dave Täht <[email protected]> wrote: > > > On 1/5/16 11:29 AM, Steinar H. Gunderson wrote: > > On Tue, Jan 05, 2016 at 10:57:13AM -0800, Dave Täht wrote: > >> Context switch time is probably one of the biggest hidden nightmares in > >> modern OOO cpu architectures - they only go fast in a straight line. I'd > >> love to see a 1ghz processor that could context switch in 5 cycles. > > > > It's called hyperthreading? ;-) > > > > Anyway, the biggest cost of a context switch isn't necessarily the time used > > to set up registers and such. It's increased L1 pressure; your CPU is now > > running different code and looking at (largely) different data. > > +10. > > A L1/L2 Icache dedicated to interrupt processing code could make a great > deal of difference, if only cpu makers and benchmarkers would make > CS time something we valued. > > Dcache, not so much, except for the intel architectures which are now > doing DMA direct to cache. (any arms doing that?) > > > /* Steinar */ > > > _______________________________________________ > Bloat mailing list > [email protected] > https://lists.bufferbloat.net/listinfo/bloat
Intel has some new Cache QoS stuff that allows configuring how much cache is allowed per context. But of course it is only on the newest/latest/unoptinium _______________________________________________ Bloat mailing list [email protected] https://lists.bufferbloat.net/listinfo/bloat
