On 2018-11-23, 08:33, "Dave Taht" <[email protected]> wrote:
Back in the day, I was a huge fan of async logic, which I first
encountered via caltech's cpu and later the amulet.
https://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU
...
I've never really understood why it didn't take off, I think, in part,
it doesn't scale to wide busses well, and that centrally clocked designs
are how most engineers and fpgas and code got designed since. Anything
with delay built into it seems hard for EEs to grasp.... but I wish I
knew why, or had the time to go play with circuits again at a reasonable
scale.
At the time, I was told the objections they got were that it uses about 2x the
space for the same functionality, and space usage is approximately linear with
the chip cost, and when under load you still need reasonable cooling, so it was
only considered maybe worthwhile for some narrow use cases.
I don't really know enough to confirm or deny the claim, and the use cases may
have gotten a lot closer to a good match by now, but this was the opinion of at
least some of the people involved with the work, IIRC.
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