> On Nov 27, 2018, at 8:09 PM, Dave Taht <[email protected]> wrote:
>
> I wish I knew of a mailing list where I could get a definitive answer
> on "modern problems with async circuits", or an update on the kind of
> techniques the new AI chips were using to keep their power consumption
> so low. I'll keep googling.
I’d be interested in knowing this as well. This gives some examples of async
circuits:
https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/lect_12.pdf
<https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/lect_12.pdf>
Page 43, “Bottom Line” mentions that asynchronous design has “some delay
matching / overhead issues”. Apparently delay matching means getting the signal
outputs on two separate paths to arrive at the same time(?) Presumably overhead
refers to the 2x space on the die previously mentioned, for completion
detection. Pages 23-25 on “data-bundling constraints” might also highlight some
other challenges. Some more current material would be interesting though...
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