On Mon, 14 Sep 2026 07:13:13 GMT, Fei Yang <[email protected]> wrote:
>> Improve startup and warmup time by making optimized native code for an >> application instantly available when the HotSpot Java Virtual Machine >> starts. Achieve this by compiling application code to native code in a >> training run, storing the native code in the [AOT >> cache](https://openjdk.org/jeps/483#Description) for use in subsequent >> production runs. >> >> More details in the [JEP](https://openjdk.org/jeps/544). >> >> --------- >> - [x] I confirm that I make this contribution in accordance with the >> [OpenJDK Interim AI Policy](https://openjdk.org/legal/ai). > > src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp line 753: > >> 751: ZSetupArguments setup_arguments(masm, stub); >> 752: __ la(t1, RuntimeAddress(stub->slow_path())); >> 753: __ jalr(t1); > > Or simply: `__ rt_call(stub->slow_path());`, which will be more consistent > with other places. > There is a similar one in file gc/g1/g1BarrierSetAssembler_riscv.cpp. > Reference add-on change: > > diff --git a/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp > b/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp > index abcf69e2df09a..aa03a90de60e7 100644 > --- a/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp > +++ b/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp > @@ -324,8 +324,7 @@ static void > generate_c2_barrier_runtime_call(MacroAssembler* masm, G1BarrierStub > __ mv(c_rarg0, arg); > } > __ mv(c_rarg1, xthread); > - __ mv(t1, runtime_path); > - __ jalr(t1); > + __ rt_call(runtime_path); > } > > void G1BarrierSetAssembler::g1_write_barrier_pre_c2(MacroAssembler* masm, > diff --git a/src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp > b/src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp > index 9fbc59fe5ce39..11f2585dbe814 100644 > --- a/src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp > +++ b/src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp > @@ -749,8 +749,7 @@ void > ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, Z > { > SaveLiveRegisters save_live_registers(masm, stub); > ZSetupArguments setup_arguments(masm, stub); > - __ mv(t1, stub->slow_path()); > - __ jalr(t1); > + __ rt_call(stub->slow_path()); > } > > // Stub exit Thank you @RealFYang, I will do that. Please, note, this PR disabled `aotCode/*` tests on RISC-V because they expect AOT code to be present. See [test/jtreg-ext/requires/VMProps.java](https://github.com/openjdk/jdk/pull/30778#diff-4ba08b1eb8d93e6abafaafff34e049ed4638d3ea2318c9e597f6051ac6ebe575). Also `AOTCodeCaching` is switched off for RISC-V in `AOTCodeCache::enable_caching()`. ------------- PR Review Comment: https://git.openjdk.org/jdk/pull/30778#discussion_r4008714027
