Hi,
Sorry, I suppose I should attach a question to this. Glenn mentioned
that I might run into timing errors when I run the iBOB at full speed
like this. Can this be solved by increasing the delays or adding
delays? Or have I missed a key parameter?
Thanks,
Matthew
On Apr 29, 2009, at 11:55 AM, Matthew Stevenson wrote:
Hi,
I'm attempting to build a 512 channel spectrometer on an iBOB. The
desired bandwidth is 1GHz, so the ADC is clocked at 1GHz with
interleaving on, and the FPGA is clocked at 250MHz. In XSG core
config, the clock source is set as adc0_clk.
This is the error I get:
ERROR:Pack:1653 - At least one timing constraint is impossible to
meet because
component delays alone exceed the constraint. A physical timing
constraint
summary will appear in the map report. This summary will show a
MINIMUM net
delay for the paths. For more information about the Timing
Analyzer, consult
the Xilinx Timing Analyzer Reference manual. For more
information on TRCE,
consult the Xilinx Development System Reference Guide "TRACE"
chapter.
And here is the timing report:
Section 11 - Timing Report
--------------------------
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
--------------------------------------------------------------------------------
Constraint | Requested |
Actual | Logic
|
| | Levels
--------------------------------------------------------------------------------
| 2.000ns |
0.000ns | N/A
--------------------------------------------------------------------------------
NET "opb_ethlite_phy_rx_clk_IBUF" PERIOD | 40.000ns |
2.417ns | 1
= 40 ns HIGH 14 ns |
| |
--------------------------------------------------------------------------------
| 2.000ns |
0.000ns | N/A
--------------------------------------------------------------------------------
NET "opb_ethlite_phy_tx_clk_IBUF" PERIOD | 40.000ns |
2.140ns | 3
= 40 ns HIGH 14 ns |
| |
--------------------------------------------------------------------------------
NET "rfi_spectrometer_512_mrk2_adc/rfi_sp | N/A | N/
A | N/A
ectrometer_512_mrk2_adc/adc_clk_buf" PERI |
| |
OD = 4 ns HIGH 50% |
| |
--------------------------------------------------------------------------------
* PERIOD analysis for net "rfi_spectrometer | 4.000ns |
8.368ns | 39
_512_mrk2_adc/rfi_spectrometer_512_mrk2_a |
| |
dc/adc_clk_dcm" derived from NET "rfi_sp |
| |
ectrometer_512_mrk2_adc/rfi_spectrometer_ |
| |
512_mrk2_adc/adc_clk_buf" PERIOD = 4 ns H |
| |
IGH 50% duty cycle corrected to 4 nS HI |
| |
GH 2 nS |
| |
--------------------------------------------------------------------------------
| 0.452ns |
0.100ns | N/A
--------------------------------------------------------------------------------
| 0.853ns |
0.100ns | N/A
--------------------------------------------------------------------------------
| 10.000ns |
2.337ns | 0
--------------------------------------------------------------------------------
| 6.000ns |
0.932ns | 1
--------------------------------------------------------------------------------
TS_dcm_clk_s = PERIOD TIMEGRP "dcm_clk_s" | N/A | N/
A | N/A
9.4 ns HIGH 50% |
| |
--------------------------------------------------------------------------------
| N/A |
1.586ns | 0
--------------------------------------------------------------------------------
| N/A | N/
A | N/A
--------------------------------------------------------------------------------
| N/A |
0.628ns | 0
--------------------------------------------------------------------------------
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 9.400ns |
5.011ns | 17
"dcm_0_dcm_0_CLK0_BUF" TS_dcm_clk_s HIGH |
| |
50% |
| |
--------------------------------------------------------------------------------
1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate
that the
constraint does not cover any paths or that it has no requested
value.
