Hi, Matthew,
On Apr 29, 2009, at 11:59 , Matthew Stevenson wrote:
Sorry, I suppose I should attach a question to this. Glenn
mentioned that I might run into timing errors when I run the iBOB
at full speed like this. Can this be solved by increasing the
delays or adding delays? Or have I missed a key parameter?
Thanks,
Matthew
On Apr 29, 2009, at 11:55 AM, Matthew Stevenson wrote:
---------------------------------------------------------------------
-----------
Constraint | Requested |
Actual | Logic
|
| | Levels
---------------------------------------------------------------------
-----------
* PERIOD analysis for net "rfi_spectrometer | 4.000ns |
8.368ns | 39
_512_mrk2_adc/rfi_spectrometer_512_mrk2_a |
| |
dc/adc_clk_dcm" derived from NET "rfi_sp |
| |
ectrometer_512_mrk2_adc/rfi_spectrometer_ |
| |
512_mrk2_adc/adc_clk_buf" PERIOD = 4 ns H |
| |
IGH 50% duty cycle corrected to 4 nS HI |
| |
GH 2 nS |
| |
---------------------------------------------------------------------
-----------
You'll need to find the signal path that has 39 (!) levels of logic
from one flip flop to the next and then try to pipeline it somehow.
Looking in the system.twr file can provide clues.
Dave
