Hi list,
I've been bitten a couple of times with a problem in the toolchain or
Xilinx tools. When you edit e.g. a BlackBox or pcore VHDL file, then
during the next full design recompile the Xilinx tools do not always
notice that the VHDL actually has changed and instead uses some
cached/preassembled old and outdated version.
So the fixed design bugs magically do not disappear from the final
bitstream ;-)
I thought this new bee_xps.fig/.m and gen_xps_files could be useful to
others on the list.
The changes add a "Make Clean" entry to bee_xps.
The Make Clean will clean 'implementation' and 'sysgen' directories, and
remove the (*.*.bac=>*.*-autogenerated) *.mhs, *.mss, *.ucf, *.xps files:
http://www.metsahovi.fi/~jwagner/iBob/toolchain/xps_library/
cheers,
- Jan
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Helsinki University of Technology
Dept. of Metsähovi Radio Observatory
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