Hi, Jan,
I vaguely remember some xst caching problem from the past and ended
up adding...
export XST_CACHE="${HOME}/.xst_cache"
...to my .bashrc. That might have been to avoid some permissions
issue with the default xst cache location, though, and not related to
your particular problem.
It sounds like the xilinx tools have (or are given) some missing/
broken dependencies. Your make clean sounds like a very thorough, if
not pinpointed :-), solution.
Thanks,
Dave
On Apr 18, 2008, at 4:24 , Jan Wagner wrote:
Hi list,
I've been bitten a couple of times with a problem in the toolchain
or Xilinx tools. When you edit e.g. a BlackBox or pcore VHDL file,
then during the next full design recompile the Xilinx tools do not
always notice that the VHDL actually has changed and instead uses
some cached/preassembled old and outdated version.
So the fixed design bugs magically do not disappear from the final
bitstream ;-)
I thought this new bee_xps.fig/.m and gen_xps_files could be useful
to others on the list.
The changes add a "Make Clean" entry to bee_xps.
The Make Clean will clean 'implementation' and 'sysgen'
directories, and remove the (*.*.bac=>*.*-autogenerated) *.mhs,
*.mss, *.ucf, *.xps files:
http://www.metsahovi.fi/~jwagner/iBob/toolchain/xps_library/
cheers,
- Jan
--
****************************************************
Helsinki University of Technology
Dept. of Metsähovi Radio Observatory
http://www.metsahovi.fi/~jwagner/
Work +358-9-256-4424
