Hi all. I am still fighting with the timing errors at 200 MHz. I have a design with most of the fpga full, so that may be a problem. What I have are three persistent errors:
1) a software register to a xaui port (tx_enable) 2) an internal xaui block path 3) a PFB coefficient generator timing error I've attached the timing report info. Any suggestions on getting the pfb to meet timing? How about tweaking the build parameters? I don't know where to go to do that, but I'm willing to try with a pointer or two... I'm not too concerned about the software register, as it just turned on once, and left on, so propagation delays shouldn't really be a problem. I took Glenn Jones' advice and decoupled everything with delays with register retiming, and that got most of the errors out of my own logic. Just these three remain. Any help would be appreciated! I've also included the model file for fun. John
<<attachment: Timing_errors.zip>>
