John, It looks like you have many more than 3 problems from the timing reports you attached. (In the future, please send twr or twx files, the weird PDF printouts are very hard to read). Regarding the TXenable, it may be routing from a bit of the register to a delay, and then fanning out from that delay to both XAUIs, thus forcing a long connection that uses up fast resources. Try using one bit of the register for each XAUI. But like you said I wouldnt worry about such an error since the software register wont be changing much. Do you need to dynamically control the FFT shifting? I would try to build with FFT shift hardwired. Also, try adding a delay with register retiming on that software register. I think at this point though, I would start cutting out auxillary features until it builds without timing errors, and then maybe compromise in some places. Glenn
On 4/29/08, John Ford <[email protected]> wrote: > Hi all. I am still fighting with the timing errors at 200 MHz. I have a > design with most of the fpga full, so that may be a problem. What I have > are three persistent errors: > > 1) a software register to a xaui port (tx_enable) > > 2) an internal xaui block path > > 3) a PFB coefficient generator timing error > > I've attached the timing report info. Any suggestions on getting the pfb > to meet timing? How about tweaking the build parameters? I don't know > where to go to do that, but I'm willing to try with a pointer or two... > > I'm not too concerned about the software register, as it just turned on > once, and left on, so propagation delays shouldn't really be a problem. > > I took Glenn Jones' advice and decoupled everything with delays with > register retiming, and that got most of the errors out of my own logic. > Just these three remain. > > Any help would be appreciated! > > I've also included the model file for fun. > > > John > >
