Hi Glenn,
The ADC interface core has an embedded DCM.
Regarding your other question about accessing the DCM lock signal, it's not
exposed anywhere in the Simulink flow, but they are available from the MHS.
It has been suggested that we should provide the lock signal as an output
from the XSG Core Config block, which sounds like a good idea to me and I
will work on that.
If you need the lock signals before I can get that done, probably the easiest
way to get them would be to add a GPIO input yellow block, but modify the MHS
to connect them to the lock signals rather than external ports.
Thanks,
Henry
G Jones wrote:
After doing some digging, I am now confused about the clocks on the iBOB.
Specifically, I thought the ADC clock was passed through a DCM to
clean it up before use, but it looks like this is not the case. Can
someone confirm? I see these lines in the system.mhs that give me this
impression:
PORT adc0_clk = adc0_clk
BEGIN fixedPFBspecTest
PARAMETER INSTANCE = fixedPFBspecTest_XSG_core_config
PARAMETER HW_VER = 1.00.a
PORT clk = adc0_clk
And the adc0_clk signal does not go to any of the DCMs.
I have built a spectrometer that meets timing, but the output is
sensitive to the sample clock speed, so I am trying to track down the
problem.
Glenn
On 4/30/08, G Jones <[email protected]> wrote:
Hello,
Is it possible to access the bits indicating if a DCM is locked from
within CASPER? Where should I look if I were to add this
functionality?
Thank you,
Glenn
