Hi, Henry,
Hope you're enjoying our visit!
On May 1, 2008, at 0:40 , Henry Chen wrote:
It has been suggested that we should provide the lock signal as an
output
from the XSG Core Config block, which sounds like a good idea to me
and I
will work on that.
Not just a lock signal, but also a "clocks ok" signal to indicate
that the startup software has "synced" the two incoming clocks from
the ADC chips. The locked signal, while useful after the "sync-up"
step, will be bouncing around during said "sync-up" step. Maybe the
"clocks ok" signal and the DCM loacked signal could be ANDed together
and come out as a single signal?
Would the lock signals from all the DCMs appear as outputs from the
XSG block or would it be just the lock signal from the main DCM used
to drive the sysgen part of the design?
Dave
