> Matt, > > sorry, I had >> iii) external clock input to BEE was improved by Pierre & Henry and >> others, > then edited it > > should have left it ! > > thanks, > > Mel. > > > On 5/2/08, Matt Dexter <[email protected]> wrote: >> Mel, >> >> Don't forget the effort we put in to deliver clean external clocks to >> Beamformer's BEE2s. This scheme is an upgrade to the prototype scheme >> I got from the BWRC folks.
Randy and Jason also designed a clock driver modification to allow the ibob to cleanly drive the bee2 clock input. It sort-of works if you just connect the ibob output to the bee2 input, but not reliably. With the clock mod, they were able to stream simple one-path data (a counter value) from an ibob, through the bee, and back to the ibob successfully and continuously. John >> >> >> Matt >> >> >> On Fri, 2 May 2008, melvyn wright wrote: >> >> > Hi Matt, >> > >> > >> > >> > On 5/2/08, Matt Dexter <[email protected]> wrote: >> > > Didn't Aaron Parsons find that the BEE2's inter-FPGA buses have >> > > particular clock frequencies were it would work and others that it >> would >> > > not ? >> > > >> > > As I understood it there was some question about the on-board >> signal >> > > integrity of those signals. I don't know if the root problem was >> > > identified or not. >> > >> > As I remember it, >> > i) the inter-FPGA buses only worked well with the internal clock, >> > ii) At some freqs they worked with external clock >> > iii) external clock input to BEE was improved by Pierre & Henry. >> > iv) Arron and Oren decided to use only xaui chip-chip connections >> > >> > Needs to to clearly stated by experts for future BEE2 users >> > >> > Mel. >> > >> > > >> > >> > > >> > > >> > > On Fri, 2 May 2008, David MacMahon wrote: >> > > >> > > > Hi, Jason, >> > > > >> > > > I've had similar experiences when sending time domain data from >> two >> > > > IBOBs to one other FPGA (in this case it was non-CASPER >> hardware: the >> > > > F board of the ATA/RAL correlator). I found that the XAUI links >> and >> > > > accompanying async fifos can have slightly different latencies. >> > > > >> > > > Could this be the cause of your misaligned data streams? >> > > > >> > > > Dave >> > > > >> > > > On May 2, 2008, at 6:27 , Jason Ray wrote: >> > > > > All, >> > > > > >> > > > > Randy and I are closing in one completing phase 1 of our >> pulsar >> > > > > machine. We have two iBOB samplers streaming samples over >> XAUI >> > > > > into the BEE2's FPGA1 and FPGA3, where the pfb & fft take >> place. >> > > > > Then we're using the inter-chip connections to pass the FFT >> bin >> > > > > values over to FPGA2 where the two streams are combined and >> then >> > > > > things like stokes, scale/offset, vacc, data packing, and 10Ge >> > > > > happen. The ADC clock is set to 800MHz and we're generating a >> > > > > 100MHz clock signal on each iBOB and piping it out of an SMA >> GPIO >> > > > > to the BEE2, which is set up to use usr_clk2x. >> > > > > >> > > > > The problem we're working on right now is that it seems the >> data >> > > > > "pipes" from the FPGA1 and FPGA3 are not aligned properly when >> they >> > > > > are received in FPGA2. We've been looking at things like the >> > > > > propagation delay differences between the two paths due to >> trace >> > > > > routing to make an educated guess about what to set the phase >> > > > > delays to (so far on the receive end only), but we have not >> had >> > > > > much luck. >> > > > > >> > > > > We believe the two data pipes aren't aligned because the two >> FFT >> > > > > syncs aren't aligned. We have previously been AND-ing the two >> > > > > syncs together to make a combined sync in FPGA2. We saw some >> > > > > peculiar behavior with the BEE2 running at 100Mhz but it >> worked >> > > > > about 50% of the time. However, when we switched to 200MHz, >> the >> > > > > combined sync never happens. We added a software register to >> > > > > select a mux that allows us to either choose to AND the syncs >> or OR >> > > > > them. Whenever AND is selected it never happens. Whenever OR >> is >> > > > > selected is (obviously) happens every time. This seems to be >> a >> > > > > fairly clear indicator that the two streams aren't aligned >> properly. >> > > > > >> > > > > Has anyone had any success with using all 138 inter-chip >> > > > > connections from two corner FPGAs, and getting them aligned >> > > > > properly in the third common FPGA, at 200MHz? >> > > > > >> > > > > Thanks in advance! >> > > > > Jason >> > > > > >> > > > > >> > > > > >> > > > >> > > > >> > > > >> > > >> > > >> > >> >
