On May 15, 2008, at 9:22 , Dan Werthimer wrote:
this problem of non-repeat of power spectra
might be a problem with how often you put in a sync pulse.
it might also be a problem that your test pattern is
not a multiple of pfb taps * fft length.
Hi, Dan, while these ideas can explain odd behaviors, I think they
would affect the design regardless of clock frequency (so long as
it's stays in reasonable range).
One thing to double check, Glenn, is that the design is really
getting built for the clock frequency you think it is. When clocking
in through the ADC blocks, the clock frequency needs to be specified
in the parameters of the ADC block(s). In this case, the clock
frequency in the XSG block is ignored. Given that your design does
run at 1024 MHz ADC clock (but not 1023 MHz ADC clock), however, I
would guess that you are already doing this correctly.
If you have two ADC cards, you could try swapping them. Maybe
something has gone bad with the current ADC0's clock signal path
integrity? I know it's a long shot, but this problem sounds rather
odd. As far as I know, an design built for one frequency should work
fine at a slower (but not *too* slow) frequency unless there are some
sort of transmission line effects (external to the FGPA) that make it
work better/worse at different frequencies.
Dave
