Hi Glen,
Since you are using a low phase noise clock and your design misbehaves
at low freq,
it's not a clock jitter problem.
but since you asked,
the FPGA DCM clock jitter depends on input clock jitter (the clock you
send to the ADC),
and power supply noise and decoupling, which the tools don't
know about. i think the tools assume that the DCM input clock is
perfect.
i suggest we chat on the phone some time. i'm free after 1 PM, at
510-418-0546.
perhaps others in our group here can join in and we can brainstorm.
dan
G Jones wrote:
As I said, I have chosen the sync pulse very carefully to ensure that
everything lines up and is static with every spectrum. Also, as Dave
suggested, I think that even if this were not the case, the design
should not depend on clock frequency.
I am not using the ADC to sample, only as a clock source. I did indeed
make sure I built with the ADC clock set to 1024 MHz. I have two iBOBs
and two ADCs and have seen the problem with both.
The clock jitter sounds like the most reasonable explanation, but I
have tried many frequencies, including very low frequencies (down to
50 or 100 MHz going into the ADC) and still see similar behavior. Thus
it seems that if jitter were causing a timing violation, it would
disappear with long clock periods. Incidentally, if I were having
jitter problems, what would be the recommended course of action? I am
using a good quality HP signal generator as a clock source. Would
turning up the amplitude help?
Thanks for the suggestions,
Glenn
On 5/15/08, Dan Werthimer <[email protected]> wrote:
glen,
another possibility is that the FPGA doesn't meet
timing because there's clock jitter.
if you compile for 250 MHz (4 nS clock), and
there's 1 nS P-P of clock jitter, then the FPGA sometimes
sees a 3.5 nS clock, and sometimes sees a 4.5 nS clock,
and the shorter 3.5 nS clock violates timing.
does is work reliably at low clock frequencies?
if so, it's not a clock jitter problem.
dan
Vinayak Nagpal wrote:
If I understand correctly Glenn is not sampling data using the ADC and
using a data source internal to the FPGA. Any transmission line effects
external to the FPGA may cause clock glitches etc but those should not
affect the results because the clock to all blocks should glitch together.
Such a problem should arise only when the clock distribution network
inside the FPGA is doing something funny. That this should happen and
synth/par tools not report it - is indeed a long shot.
On May 15, 2008, at 9:47 AM, David MacMahon wrote:
On May 15, 2008, at 9:22 , Dan Werthimer wrote:
this problem of non-repeat of power spectra
might be a problem with how often you put in a sync pulse.
it might also be a problem that your test pattern is
not a multiple of pfb taps * fft length.
Hi, Dan, while these ideas can explain odd behaviors, I think they would
affect the design regardless of clock frequency (so long as it's stays in
reasonable range).
One thing to double check, Glenn, is that the design is really getting
built for the clock frequency you think it is. When clocking in through the
ADC blocks, the clock frequency needs to be specified in the parameters of
the ADC block(s). In this case, the clock frequency in the XSG block is
ignored. Given that your design does run at 1024 MHz ADC clock (but not
1023 MHz ADC clock), however, I would guess that you are already doing this
correctly.
If you have two ADC cards, you could try swapping them. Maybe something
has gone bad with the current ADC0's clock signal path integrity? I know
it's a long shot, but this problem sounds rather odd. As far as I know, an
design built for one frequency should work fine at a slower (but not *too*
slow) frequency unless there are some sort of transmission line effects
(external to the FGPA) that make it work better/worse at different
frequencies.
Dave
