All,
As some of you know, Randy and I have been recently working on trying
to get the interchip connections to work properly, utilizing the
packed registers, phase delays, etc to get synchronized data into
FPGA2. We have a question regarding the build times for BEE2 designs
that use these interchip connections.
In FPGAs 1 and 3, we have: XAUI ---> PFB ---> FFT ---> interchip connections
Both designs are absolutely identical, with the exception being the
directions of the interchip connection GPIO blocks. The design for
FPGA3 (using right links to FPGA2) takes about 10-12 hours to
build. However, the design for FPGA1 (using left links to FPGA2)
takes about 25 hours to build! Has anyone experienced this kind of
variation in build times with the only difference being the GPIO direction?
Thanks,
Jason
