I haven't had exactly this problem, but I have had designs meet timing and then changing just the slightest thing makes it miss timing by a lot. I think the place and route is sort of heuristic, so just by chance it gets an easy job some days and other days it spends hours going in the wrong direction. Routing from one side of the chip to the other seems like something that could easily cause this, but that's just speculation on my part. Glenn
On Thu, Jun 12, 2008 at 1:29 PM, Jason Ray <[email protected]> wrote: > All, > > As some of you know, Randy and I have been recently working on trying to get > the interchip connections to work properly, utilizing the packed registers, > phase delays, etc to get synchronized data into FPGA2. We have a question > regarding the build times for BEE2 designs that use these interchip > connections. > > In FPGAs 1 and 3, we have: XAUI ---> PFB ---> FFT ---> interchip > connections > > Both designs are absolutely identical, with the exception being the > directions of the interchip connection GPIO blocks. The design for FPGA3 > (using right links to FPGA2) takes about 10-12 hours to build. However, the > design for FPGA1 (using left links to FPGA2) takes about 25 hours to build! > Has anyone experienced this kind of variation in build times with the only > difference being the GPIO direction? > > Thanks, > Jason > > > >
