Yes, I believe you are correct, that the way our DCMs are configured,
the lower guaranteed limit is 24MHz (CLK0, CLK90, CLK180 or CLK270 DCM
outputs). Perhaps you could use the CLKDV output of the DCMs... this
will let you clock it down to 1.5MHz. I don't think there's any
fundamental lower limit in the fabric for clocking things slowly.
Nevertheless, I've had my 200MHz F engine design clocked down to 10MHz
for debugging and I still got sensible data out of it. Maybe I just
got lucky.
Jason
On 24 Oct 2008, at 16:10, Andrew Siemion wrote:
I may be wrong, but I believe the lowest clock officially supported
by the
dcms is 24MHz (sampling @ 96MHz).
- andrew
On 10/24/08 1:29 PM, "Jason Manley" <[email protected]> wrote:
I have successfully used an IBOB down to 10MHz (ie ADCs at 40MHz).
Jason
On 24 Oct 2008, at 13:27, Randy McCullough wrote:
All,
We're dealing with a design which uses an iBOB and an iADC as
a front end "sampler" which operates typically with an 800MHz
sample clk (interleaved), derives it's logic clock from the ADC at
200MHz and concatenates and streams the low-order samples
through XAUI port 0 and the high-order samples through XAUI
port 1.
We'd like to try simply cranking the sample clk down; thereby
effectively altering our sampled BW (i.e., 800MHz, 400MHz,
200MHz, 100MHz, etc...). Since our logic clk is always 1/4
of our sample clk, and the XAUI ports derive their internal clks
from the logic clk, what is the lowest practical speed at which
we can run things without wrecking the XAUI ports' operation.
Or, put another way, what is the lowest logic clock rate we
can use on an iBOB and still maintain reliable XAUI trans-
missions?
Lastly, are there any other aspects of an iBOB/iADC design
which might place a lower constraint on our speed --such as
the ADC chip, LWIP, etc., etc., etc.?
Thanks,
Randy
