Hi Randy, We have just sampled at higher frequency and discarded extra samples. I think sampling frequency was 512 MHz and output frequency 32 MHz.
In our case clock was generated by a Maxim or Analog Devices PLL clock generator evaluation kit which costs about 100 dollars.
It is a good idea to have a low-pass filter in the ADC input, saw some indication that higher-frequency noise got through.
Cheers, Jouko "Life is pretty simple: You do some stuff. Most fails. Some works. You do more of what works. If it works big, others quickly copy it. Then you do something else. The trick is to do something else." On Fri, 24 Oct 2008, Randy McCullough wrote:
All, We're dealing with a design which uses an iBOB and an iADC as a front end "sampler" which operates typically with an 800MHz sample clk (interleaved), derives it's logic clock from the ADC at 200MHz and concatenates and streams the low-order samples through XAUI port 0 and the high-order samples through XAUI port 1. We'd like to try simply cranking the sample clk down; thereby effectively altering our sampled BW (i.e., 800MHz, 400MHz, 200MHz, 100MHz, etc...). Since our logic clk is always 1/4 of our sample clk, and the XAUI ports derive their internal clks from the logic clk, what is the lowest practical speed at which we can run things without wrecking the XAUI ports' operation. Or, put another way, what is the lowest logic clock rate we can use on an iBOB and still maintain reliable XAUI trans- missions? Lastly, are there any other aspects of an iBOB/iADC design which might place a lower constraint on our speed --such as the ADC chip, LWIP, etc., etc., etc.? Thanks, Randy
