Hi Wan I had a look at your design and noticed the following;
* The output of the FFT is complex data. You need to convert this into real and imaginary parts if it is to make sense. Use a c_to_ri from the Misc section of the library. * You need to put "Gateway Out" blocks on all signals from Xilinx blocks that go to 'normal' Simulink blocks. This means that all inputs to Scope blocks from System Generator blocks need to go through a "Gateway Out" block. * Please also re-read the memo Henry suggested on the use of syncs in the CASPER library. Your sync period is too small relative to the size of your FFT and PFB. * Also note that the output sync from the FFT will show you where your spectrum begins so you may want to look at that with the scope you use to look at the FFT data too. Hope this helps. Cheers Andrew 2008/11/4 <[email protected]> > Hi all: > > I build a very basic module with PFB and FFT. But the output looks not > right. Anybody has anyidea? What's wrong with it? > The attached is the mdl file. > > Thanks. > > Wan >
