Re: [casper] Casper library basic setup

[Henry Chen]

Hi Wanxiang,

If the sync you're setting is the simulation input to the ADC block,
then it's treated as the reset to your sync generator, not the sync
itself. In this case, when you set it to 1 you're just always holding
down the reset to your counter, so you're actually never generating
your sync pulse. In this case, the internal counters of the DSP blocks
just run on their own, so you still get output.

Regarding the output, what do you find wrong about it? Can you be more
specific? A suggestion: look at the sync pulse output from the FFT
rather than the input. Note that the power block you're using has a
latency of 5 (3 in the multiplier, 2 in the adder), so you need to
realign the sync pulse with the power before looking at it in a Scope.

Thanks,
Henry

wan.ch...@csiro.au wrote:

Hi Andrew:

Another strange thing is I still get the output no matter I set Sync to "0" or "1". I think Sync could be considered as a sync reset signal. I should not get anything out if I fix the sync to "1". Wan

------------------------------------------------------------------------
*From:* Andrew Martens [mailto:martens.and...@gmail.com]
*Sent:* Wednesday, 5 November 2008 7:56 PM
*To:* Cheng, Wan (ATNF, Marsfield)
*Cc:* casper@lists.berkeley.edu
*Subject:* Re: [casper] Casper library basic setup

Hi Wan

Also remember that you have a PFB so (from the memo) you should remember to include the number of taps in your calculation.

e.g 2 order-2 reorder blocks, order-9 unscrambler, 4 input, 2048 channels, 2 tap PFB

min sync = 2x(2x9x2048/4) = 9216x2

Good luck
Andrew

2008/11/5 <wan.ch...@csiro.au>

    Hi Andrew:

Thanks for your help. According the sync_memo: My example is: 2 order-2 reorder blocks, order-9 unscrambler, 4

    input, 2048 channels.

minimum sync period = 2*9*2048/4 = 9216. And I set the counter to 9215. I guess the sync period is all right. Wan

    ------------------------------------------------------------------------
    *From:* Andrew Martens [mailto:martens.and...@gmail.com
    <mailto:martens.and...@gmail.com>]
    *Sent:* Tuesday, 4 November 2008 6:07 PM
    *To:* Cheng, Wan (ATNF, Marsfield)
    *Cc:* casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>
    *Subject:* Re: [casper] Casper library basic setup

    Hi Wan

    I had a look at your design and noticed the following;

    * The output of the FFT is complex data. You need to convert this
    into real and imaginary parts if it is to make sense. Use a c_to_ri
    from the Misc section of the library.
    * You need to put "Gateway Out" blocks on all signals from Xilinx
    blocks that go to 'normal' Simulink blocks. This means that all
    inputs to Scope blocks from System Generator blocks need to go
    through a "Gateway Out" block.
    * Please also re-read the memo Henry suggested on the use of syncs
    in the CASPER library. Your sync period is too small relative to the
    size of your FFT and PFB.
    * Also note that the output sync from the FFT will show you where
    your spectrum begins so you may want to look at that with the scope
    you use to look at the FFT data too.

    Hope this helps.

    Cheers
    Andrew


    2008/11/4 <wan.ch...@csiro.au>

        Hi all:

I build a very basic module with PFB and FFT. But the output

        looks not right. Anybody has anyidea? What's wrong with it?
        The attached is the mdl file.

Thanks. Wan